SH7616 Datasheet, PDF (410/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
Bit 0—Illegal Carrier Detection (ICD): Indicates that PHY-LSI has detected an illegal carrier on
the line. This bit is cleared by writing 1 to it. Writing 0 to this bit has no effect.
Bit 0: ICD
Description
0
PHY-LSI has not detected an illegal carrier on the line
(Initial value)
1
PHY-LSI has detected an illegal carrier on the line
Note: If a change in the signal input from the PHY-LSI occurs before the software recognition
period, the correct information may not be obtained. Refer to the timing specification for the
PHY-LSI used.
9.2.3 EtherC Interrupt Permission Register (ECSIPR)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
— LCHNGI MPDIP ICDIP
P
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
This register enables or disables the interrupt sources indicated by the EtherC status register. Each
bit in this register enables or disables the interrupt indicated by the corresponding bit in the EtherC
status register.
Bits 31 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 2— LINK Signal Changed Interrupt Permission (LCHNGIP): Controls interrupt notification
by the LINK Signal Changed bit.
Bit 2: LCHNGIP
0
1
Description
Interrupt notification by LCHNG bit in ECSR is disabled
Interrupt notification by LCHNG bit in ECSR is enabled
(Initial value)
Rev. 2.00 Mar 09, 2006 page 384 of 906
REJ09B0292-0200