SH7616 Datasheet, PDF (467/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.11 FIFO Depth Register (FDR)
FDR specifies the depth (size) of the transmit and receive FIFOs.
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
TFD2 TFD1 TFD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
RFD2 RFD1 RFD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
Bits 31 to 11—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 10 to 8—Transmit FIFO Depth (TFD): Specifies 256 bytes to 2 kbytes in 256-byte units as the
depth (size) of the transmit FIFO. The setting cannot be changed after transmission/reception has
started.
Bits 10 to 8: TFD2 to TFD0
H'0
H'1
:
H'7
Description
256 bytes
512 bytes
:
2048 bytes
(Initial value)
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 441 of 906
REJ09B0292-0200