SH7616 Datasheet, PDF (463/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether or not transmit and receive status information reported by bits in the
EtherC/E-DMAC status register is to be indicated in the corresponding descriptor. The bits in this
register correspond to EtherC/E-DMAC status register EESR[15 to 0]. When a bit is cleared to 0,
the transmit status (EESR[15 to 8]) is indicated in the TFE bit of the transmit descriptor, and the
receive status (EESR[7 to 0]) is indicated in the RFE bit of the receive descriptor. When a bit is set
to 1, the occurrence of the corresponding source is not indicated in the descriptor. After the chip is
reset, all bits are cleared to 0.
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
RMAFCE —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
Bits 31 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Multicast Address Frame Receive (RMAF): Bit Copy Enable (RMAFCE)
Bit 7: RMAFCE
0
1
Description
Enables the RMAF bit status to be indicated in the RFS7 bit in the receive
descriptor.
Disables occurrence of corresponding source to be indicated in the RFS7 bit in
the receive descriptor.
Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
For the corresponding bit sources, see section 10.2.6, EtherC/E-DMAC Status Register (EESR).
Rev. 2.00 Mar 09, 2006 page 437 of 906
REJ09B0292-0200