SH7616 Datasheet, PDF (601/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set
number of data bytes in the receive FIFO data register (SCFRDR), and no further data has arrived
for at least 16 etu after the stop bit of the last data received.
Bit 0: DR
Description
0
Reception is in progress or has ended normally and there is no receive data left
in SCFRDR
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to DR after all the remaining receive data has been
read^*1
1
No further receive data has arrived, and SCFRDR contains fewer than the
receive trigger set number of data bytes
[Setting condition]
When SCFRDR contains fewer than the receive trigger set number of receive
data bytes, and no further data has arrived for at least 16 etu after the stop bit
of the last data received^*2
Notes: 1. All remaining receive data should be read before clearing the DR flag.
2. Equivalent to 1.6 frames when using an 8-bit, 1-stop-bit format.
etu: Elementary time unit = sec/bit
14.2.8 Serial Status 2 Register (SC2SSR)
Bit: 7
6
5
4
3
2
1
0
TLM RLM
N1
N0
MPB MPBT
EI
ORER
Initial value: 0
0
1
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R
R/W
R/W R/(W)^*
Note: * Only 0 can be written, to clear the flag.
The serial status 2 register (SC2SSR) is an 8-bit register.
SC2SSR can be read or written to at all times. However, 1 cannot be written to the ORER flag.
Also note that in order to clear this flag to 0, they must first be read as 1.
SC2SSR is initialized to H'20 by a reset, by the module standby function, and in standby mode.
Rev. 2.00 Mar 09, 2006 page 575 of 906
REJ09B0292-0200