SH7616 Datasheet, PDF (421/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.14 Illegal Frame Length Counter Register (IFLCR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit:
Initial value:
R/W:
15
IFLC15
0
R/W
14
IFLC14
0
R/W
13
IFLC13
0
R/W
12
IFLC12
0
R/W
11
IFLC11
0
R/W
10
IFLC10
0
R/W
9
IFLC9
0
R/W
8
IFLC8
0
R/W
Bit:
Initial value:
R/W:
7
IFLC7
0
R/W
6
IFLC6
0
R/W
5
IFLC5
0
R/W
4
IFLC4
0
R/W
3
IFLC3
0
R/W
2
IFLC2
0
R/W
1
IFLC1
0
R/W
0
IFLC0
0
R/W
IFLCR is a 16-bit counter that indicates the number of times transmission of a packet with a frame
length of less than four bytes was attempted during data transmission. When the value in this
register reaches H'FFFF (65,535), the count is halted. The counter value is cleared to 0 by a write
to this register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—Illegal Frame Length Count 15 to 0 (IFLC15 to IFLC0): These bits indicate the
count of illegal frame length transmission attempts.
Rev. 2.00 Mar 09, 2006 page 395 of 906
REJ09B0292-0200