SH7616 Datasheet, PDF (278/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.1.3 Pin Configuration
Table 7.1 shows the BSC pin configuration.
Table 7.1 Pin Configuration
Signal I/O
A24–A0 O
D31–D0 I/O
BS
O
CS0–CS4 O
RD/WR O
RAS
O
CAS/OE O
RD
O
WAIT
I
BRLS
I
BGR
O
CKE
O
IVECF O
DREQ0 I
DACK0 O
With Bus
Released
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Don’t care
I
O
O
O
I
O
Description
Address bus. 32 Mbytes of memory space can be specified with 25
bits
32-bit data bus. When reading or writing a 16-bit width area, use
D15–D0; when reading or writing a 8-bit width area, use D7–D0.
With 8-bit accesses that read or write a 32-bit width area, input and
output the data via the byte position determined by the lower
address bits of the 32-bit bus
Indicates start of bus cycle or monitor. With the basic interface
(device interfaces except for DRAM, synchronous DRAM), signal is
asserted for a single clock cycle simultaneous with address output.
The start of the bus cycle can be determined by this signal
Chip select. CS3 is not asserted when the CS3 space is DRAM
space
Read/write signal. Signal that indicates access cycle direction
(read/write). Connected to WE pin when DRAM/synchronous
DRAM is connected
RAS pin for DRAM/synchronous DRAM
Open when using DRAM
Connected to OE pin when using EDO RAM
Connected to CAS pin when using synchronous DRAM
Read pulse signal (read data output enable signal). Normally,
connected to the device’s OE pin; when there is an external data
buffer, the read cycle data can only be output when this signal is
low
Hardware wait input
Bus release request input
Bus grant output
Synchronous DRAM clock enable control. Signal for supporting
synchronous DRAM self-refresh
Interrupt vector fetch
DMA request 0
DMA acknowledge 0
Rev. 2.00 Mar 09, 2006 page 252 of 906
REJ09B0292-0200