SH7616 Datasheet, PDF (409/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

9.2.2 EtherC Status Register (ECSR)
Bit: 31
30
29
—
—
—
Initial value: 0
0
0
R/W: R
R
R
Section 9 Ethernet Controller (EtherC)
...
11
10
9
8
...
—
—
—
—
...
0
0
0
0
...
R
R
R
R
Bit: 7
6
5
4
3
2
—
—
—
—
— LCHNG
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R/W^*
Note: * The flag is cleared by writing 1. Writing 0 does not affect the flag.
1
MPD
0
R/W^*
0
ICD
0
R/W^*
The EtherC status register shows the internal status of the EtherC. This status information can be
reported to the CPU by means of interrupts. Individual bits are cleared by writing 1 to them. For
bits that generate an interrupt, the interrupt can be enabled or disabled by means of the
corresponding bit in the EtherC status interrupt permission register (ECSIPR).
Bits 31 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 2—LINK Signal Changed (LCHNG): Indicates that the LNKSTA signal input from the PHY-
LSI has changed from high to low, or from low to high. This bit is cleared by writing 1 to it.
Writing 0 to this bit has no effect.
Bit 2: LCHNG Description
0
LNKSTA signal change has not been detected
(Initial value)
1
LNKSTA signal change (high-to-low or low-to-high) has been detected
Notes: 1. The current link status can be checked by referencing the LMON bit in the PHY
interface status register (PSR).
2. Signal variation may be detected when the LNKSTA function is selected by the port A
control register (PACR) of the pin function controller (PFC).
Bit 1—Magic Packet Detection (MPD): Indicates that a Magic Packet has been detected on the
line. This bit is cleared by writing 1 to it. Writing 0 to this bit has no effect.
Bit 1: MPD
0
1
Description
Magic Packet has not been detected
Magic Packet has been detected
(Initial value)
Rev. 2.00 Mar 09, 2006 page 383 of 906
REJ09B0292-0200