SH7616 Datasheet, PDF (566/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 12 16-Bit Free-Running Timer (FRT)
12.7.4 Internal Clock Switching and Counter Operation
FRC will sometimes begin incrementing because of the timing of switching between internal
clocks. Table 12.4 shows the relationship between internal clock switching timing (CKS1 and
CKS0 bit rewrites) and FRC operation.
When an internal clock is used, the FRC clock is generated when the falling edge of an internal
clock (created by dividing the system clock (φ)) is detected. When a clock is switched to high
before the switching and to low after switching, as shown in case 3 in table 12.4, the switchover is
considered a falling edge and an FRC clock pulse is generated, causing FRC to increment. FRC
may also increment when switching between an internal clock and an external clock.
Table 12.4 Internal Clock Switching and FRC Operation
Timing of Rewrite of
No. CKS1 and CKS0 Bits
1 Low-to-low switch
FRC Operation
Clock before
switching
Clock after
switching
FRC clock
2 Low-to-high switch
FRC
Clock before
switching
Clock after
switching
FRC clock
N
Rewrite of CKS bit
N+1
FRC
N
N+1
N+2
Rewrite of CKS bit
Rev. 2.00 Mar 09, 2006 page 540 of 906
REJ09B0292-0200