SH7616 Datasheet, PDF (74/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
[7:0]
8 bits
32 bits
16 bits
16 bits
16 bits
32 bits
CDB
XDB
YDB
MOVX.W,
31
16
MOVS.W,
MOVS.L
MOVS.W,
MOVY.W
0
MOVS.L
A0
39
32
A1
A0G
M0
A1G
M1
DSR
X0
7
0
X1
Y0
Y1
Figure 2.8 DSP Register-Bus Relationship during Data Transfers
2.3 CPU Core Instruction Features
The CPU core instructions are RISC type. The characteristics are as follows.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using
the pipeline system. One state equals 16.0 ns when operating at 62.5 MHz.
Data Length: Longword is the basic data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data.
Rev. 2.00 Mar 09, 2006 page 48 of 906
REJ09B0292-0200