SH7616 Datasheet, PDF (720/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
TIOR0L
Bit 7: Bit 6: Bit 5: Bit 4:
Channel IOD3 IOD2 IOD1 IOD0 Description
0
0
0
0
0
TGR0D Output disabled
(Initial value)
1
isoutput _{Initial output is 0 0 output at compare match}
1
0
compare
register^*1
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
1
0
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
0
TGR0D is Capture input Input capture at rising edge
1
input
source is
1
*
capture TIOCD0 pin
register^*1
Input capture at falling edge
Input capture at both edges
1
*
*
Setting prohibited
*: Don’t care
Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 Mar 09, 2006 page 694 of 906
REJ09B0292-0200