SH7616 Datasheet, PDF (496/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit 7—Acknowledge Level Bit (AL): Selects whether the DACKn signal is an active-high signal
or an active-low signal. The AL bit is initialized to 0 by a reset and in standby mode. Its value is
retained during a module standby.
Bit 7: AL
0
1
Description
DACKn is an active-low signal
DACKn is an active-high signal
(Initial value)
Bit 6—DREQn Select Bit (DS): Selects the DREQn input detection used. When 0 (level detection)
is set to bit DS, set 0 (cycle-steal mode) to the transfer bus mode bit (TB). When 0 is set to bit DS
and 1 (burst mode) is set to bit TB, system operations are not guaranteed. The DS bit is initialized
to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 6: DS
0
1
Description
Detected by level
Can be set only in cycle-steal mode
Detected by edge
(Initial value)
Bit 5—DREQn Level Bit (DL): Selects the DREQn input detection level. The DL bit is initialized
to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 5: DL
0
1
Description
When DS is 0, DREQ is detected by low level; when DS is 1, DREQ is
detected at falling edge
(Initial value)
When DS is 0, DREQ is detected by high level; when DS is 1, DREQ is
detected at rising edge
Bit 4—Transfer Bus Mode Bit (TB): Selects the bus mode for DMA transfers. When 1 (burst
mode) is set to bit TB, set 1 (edge detection) to the DREQ select bit (DS). When 1 is set to bit TB
and 0 (level detection) is set to bit DS, system operations are not guaranteed. The TB bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 4: TB
0
1
Description
Cycle-steal mode
Burst mode
(Initial value)
Rev. 2.00 Mar 09, 2006 page 470 of 906
REJ09B0292-0200