SH7616 Datasheet, PDF (731/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

17.2.7 Timer General Register (TGR)
Bit: 15
14
13
Section 17 16-Bit Timer Pulse Unit (TPU)
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture
registers. The TPU has 8 TGR registers, four for channel 0 and two each for channels 1, and 2.
TGRC and TGRD for channel 0 can also be designated for operation as buffer registers*. The
TGR registers are initialized to H'FFFF by a reset.
The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Note: * TGR buffer register combinations are TGRA–TGRC and TGRB–TGRD.
17.2.8 Timer Start Register (TSTR)
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
CST2 CST1 CST0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2.
TSTR is initialized to H'00 by a reset.
TCNT counter operation should be stopped when setting the operating mode in TMDR or the
TCNT count clock in TCR.
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 705 of 906
REJ09B0292-0200