SH7616 Datasheet, PDF (217/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
Program execution
state
Interrupt
No
generated?
Yes
NMI?
No
Yes
User break?
No
Yes
Save SR to stack
Save PC to stack
Copy accepted
interrupt level to I3–I0
Read vector number*
H-UDI
No
interrupt?
Yes
Level 15
No
interrupt?
Yes
Yes
I3 to I0 ≤
level 14?
Level 14
interrupt?
Yes
No Yes
I3 to I0 ≤
level 13?
No
Level 1 ^No
interrupt?
Yes
No Yes
I3 to I0 =
level 0?
No
Read exception
vector table
Branch to exception
service routine
I3–I0: Status register interrupt mask bits.
Note: * The vector number is only read from an external source when an external vector number is
specified for the IRL/IRQ interrupt vector number.
Figure 5.8 Interrupt Sequence Flowchart
Rev. 2.00 Mar 09, 2006 page 191 of 906
REJ09B0292-0200