SH7616 Datasheet, PDF (126/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.39 ALU Logical Operation Instructions
Instruction
PAND Sx,Sy,Dz
DCT PAND
Sx,Sy,Dz
DCF PAND
Sx,Sy,Dz
POR Sx,Sy,Dz
DCT POR
Sx,Sy,Dz
DCF POR
Sx,Sy,Dz
PXOR Sx,Sy,Dz
DCT PXOR
Sx,Sy,Dz
DCF PXOR
Sx,Sy,Dz
Operation
Sx & Sy → Dz, clear LSW
of Dz
If DC=1, Sx & Sy → Dz,
clear LSW of Dz; if 0, nop
If DC=0, Sx & Sy → Dz,
clear LSW of Dz; if 1, nop
Sx | Sy → Dz, clear LSW of
Dz
If DC=1, Sx | Sy → Dz,
clear LSW of Dz; if 0, nop
If DC=0, Sx | Sy → Dz,
clear LSW of Dz; if 1, nop
Sx ^ Sy → Dz, clear LSW
of Dz
If DC=1, Sx ^ Sy → Dz,
clear LSW of Dz; if 0, nop
If DC=0, Sx ^ Sy → Dz,
clear LSW of Dz; if 1, nop
Code
111110**********
10010101xxyyzzzz
111110**********
10010110xxyyzzzz
111110**********
10010111xxyyzzzz
111110**********
10110101xxyyzzzz
111110**********
10110110xxyyzzzz
111110**********
10110111xxyyzzzz
111110**********
10100101xxyyzzzz
111110**********
10100110xxyyzzzz
111110**********
10100111xxyyzzzz
Cycles
1
1
1
1
1
1
1
1
1
DC Bit
Update
—
—
Update
—
—
Update
—
—
Table 2.40 Fixed Point Multiplication Instructions
Instruction
PMULS
Se,Sf,Dg
Operation
MSW of Se × MSW of
Sf→Dg
Code
111110**********
0100eeff0000gg00
Cycles
1
DC Bit
—
Rev. 2.00 Mar 09, 2006 page 100 of 906
REJ09B0292-0200