SH7616 Datasheet, PDF (552/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 12 16-Bit Free-Running Timer (FRT)
Bit 1—Timer Overflow Flag (OVF): Status flag that indicates when FRC overflows (from H'FFFF
to H'0000). This flag is cleared by software and set by hardware. It cannot be set by software.
Bit 1: OVF
0
1
Description
[Clearing condition]
When OVF is read while set to 1, and then 0 is written to it
(Initial value)
[Setting condition]
When the FRC value changes from H'FFFF to H'0000
Bit 0—Counter Clear A (CCLRA): Selects whether or not to clear FRC on compare match A
(signal indicating match of FRC and OCRA).
Bit 0: CCLRA
0
1
Description
FRC clear disabled
FRC cleared on compare match A
(Initial value)
12.2.6 Timer Control Register (TCR)
Bit: 7
6
5
4
3
2
1
0
IEDG
—
—
—
—
—
CKS1 CKS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R/W R/W
TCR is an 8-bit read/write register that selects the input edge for input capture and selects the
input clock for FRC. TCR is initialized to H'00 by a reset, in standby mode, and when the module
standby function is used.
Bit 7—Input Edge Select (IEDG): Selects whether to capture the input capture input (FTI) on the
falling edge or rising edge.
Bit 7: IEDG
0
1
Description
Input captured on falling edge
Input captured on rising edge
(Initial value)
Bits 6 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 526 of 906
REJ09B0292-0200