SH7616 Datasheet, PDF (781/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 18 User Debug Interface (H-UDI)
18.2.4 Test Data Output (TDO)
The test data output pin (TDO) performs serial output of instructions and data from H-UDI
registers. Transfer is performed in synchronization with TCK. If there is no output, TDO goes to
the high-impedance state.
18.2.5 Test Reset (TRST)
The test reset pin (TRST) initializes the H-UDI asynchronously. If no signal is input, TRST is
fixed at 1 by internal pull-up.
18.3 Register Descriptions
18.3.1 Instruction Register (SDIR)
Bit: 15
14
13
12
11
10
9
8
TS3
TS2
TS1
TS0
—
—
—
—
Initial value: 1
1
1
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. H-UDI
instructions can be transferred to SDIR by serial input from TDI. SDIR can be initialized by the
TRST signal, but is not initialized by a reset or in standby mode.
SDIR defines 4 valid bits for instruction. If an instruction exceeding 4 bits is input, the last 4 bits
of the serial data will be stored in SDIR.
Operation is not guaranteed if a reserved instruction is set in this register.
Bits 15 to 12—Test Set Bits (TS3–TS0): Table 18.4 shows the instruction configuration.
Rev. 2.00 Mar 09, 2006 page 755 of 906
REJ09B0292-0200