SH7616 Datasheet, PDF (494/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
DMA channel control registers 0 and 1 (CHCR0 and CHCR1) are 32-bit read/write registers that
control the DMA transfer mode. They also indicate the DMA transfer status. Only the lower 16 of
the 32 bits are valid. They should be read and written as 32-bit values, including the upper 16 bits.
The registers are initialized to H'00000000 by a reset and in standby mode. Values are retained
during a module standby.
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 and 14—Destination Address Mode Bits 1, 0 (DM1, DM0): Select whether the DMA
destination address is incremented, decremented or left fixed (in single address mode, DM1 and
DM0 are ignored when transfers are made from a memory-mapped external device, or external
memory to an external device with DACK). DM1 and DM0 are initialized to 00 by a reset and in
standby mode. Values are retained during a module standby.
Bit 15: DM1
0
1
Bit 14: DM0
0
1
0
1
Description
Fixed destination address
(Initial value)
Destination address is incremented (+1 for byte transfer size,
+2 for word transfer size, +4 for longword transfer size, +16
for 16-byte transfer size)
Destination address is decremented (–1 for byte transfer size,
–2 for word transfer size, –4 for longword transfer size, –16
for 16-byte transfer size)
Reserved (setting prohibited)
Bits 13 and 12—Source Address Mode Bits 1, 0 (SM1, SM0): Select whether the DMA source
address is incremented, decremented or left fixed. (In single address mode, SM1 and SM0 are
ignored when transfers are made from an external device with DACK to a memory-mapped
external device, or external memory.) For a 16-byte transfer, the address is incremented by +16
regardless of the SM1 and SM0 values. SM1 and SM0 are initialized to 00 by a reset and in
standby mode. Values are retained during a module standby.
Bit 13: SM1
0
1
Bit 12: SM0
0
1
0
1
Description
Fixed source address (+16 for 16-byte transfer size)
(Initial value)
Source address is incremented (+1 for byte transfer size, +2
for word transfer size, +4 for longword transfer size, +16 for
16-byte transfer size)
Source address is decremented (–1 for byte transfer size, –2
for word transfer size, –4 for longword transfer size, +16 for
16-byte transfer size)
Reserved (setting prohibited)
Rev. 2.00 Mar 09, 2006 page 468 of 906
REJ09B0292-0200