SH7616 Datasheet, PDF (628/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
BRK = 1?
Yes
Clear RE bit to 0 in SCSCR
1. Whether a framing error or
parity error has occurred in the
receive data read from
SCFRDR can be ascertained
from the FER and PER bits in
SC1SSR.
2. When a break signal is
received, receive data is not
transferred to SCFRDR while
the BRK flag is set. However,
note that the H'00 break data
in which a framing error
occurred is stored as the last
data in SCFRDR.
No
DR = 1?
Yes
Read receive data from SCFRDR 1
No
FER = 1?
Yes
Framing error handling
2
No
PER = 1?
Yes
Parity error handling
No
All data read?
Yes
Clear ORER, BRK, DR, and
ER flags to 0
End
Figure 14.8 Sample Serial Reception Flowchart (2)
Rev. 2.00 Mar 09, 2006 page 602 of 906
REJ09B0292-0200