SH7616 Datasheet, PDF (155/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 4 Exception Handling
Table 4.3 (b) Exception Processing Vector Table (IRQ Mode)
Exception Source
Interrupt
IRQ0
IRQ1
IRQ2
IRQ3
On-chip
peripheral
module^*3
Vector
Number
64^*2
65^*2
66^*2
67^*2
0^*4
:
127^*4
Vector Table Address
Offset
H'00000100–H'00000103
H'00000104–H'00000107
H'00000108–H'0000010B
H'0000010C–H'0000010F
H'00000000–H'00000003
:
H'000001FC–H'000001FF
Vector Addresses
Table 4.3 (c) Exception Processing Vector Table (IRL Mode)
Exception Source
Vector Vector Table Address
Number Offset
Vector Addresses
Interrupt
IRL1^*1
IRL2^*1
64^*2
65^*2
H'00000100–H'00000103
H'00000104–H'00000107
VBR + (vector
number × 4)
IRL3^*1
IRL4^*1
66^*2
H'00000108–H'0000010B
IRL5^*1
IRL6^*1
67^*2
H'0000010C–H'0000010F
IRL7^*1
IRL8^*1
68^*2
H'00000110–H'00000113
IRL9^*1
IRL10^*1
69^*2
H'00000114–H'00000117
IRL11^*1
IRL12^*1
70^*2
H'00000118–H'0000011B
IRL13^*1
IRL14^*1
71^*2
H'0000011C–H'0000011F
IRL15^*1
On-chip
peripheral
module^*3
0^*4
:
127^*4
H'00000000–H'00000003
:
H'000001FC–H'000001FF
Notes: 1. When 1110 is input to the IRL3, IRL2, IRL1, and IRL0 pins, an IRL1 interrupt results.
When 0000 is input, an IRL15 interrupt results.
Rev. 2.00 Mar 09, 2006 page 129 of 906
REJ09B0292-0200