SH7616 Datasheet, PDF (863/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 22 Electrical Characteristics
CKIO
Address
upper bits
Address
lower bits
BS
CSn
RD/WR
RD
WEn ⋅
DQMxx
D31–D0
DACKn*²
T_r
T_c
t_AD
t_AD
t_BSD
t_CSD1
t_RWD
t_RWD
t_DQMD
t_WDD1
t_DON
t_DACD1
T_ap
t_AD
t_BSD
t_CSD1
t_CSD1
*¹
t_RWD
t_RSD1
t_DQMD
t_DOF
t_WDH1
t_DACD1
*¹
t_DACD1
WAIT
RAS
CAS ⋅
OE
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_CASD1
*¹
CKE
Notes: 1. Dotted line shows the case where synchronous DRAM in a different CS space is
accessed.
2. DACKn waveform when active-high is specified
Figure 22.22 Synchronous DRAM Write Bus Cycle
(RASD = 0, RCD = 1 Cycle, TRWL = 1 Cycle)
Rev. 2.00 Mar 09, 2006 page 837 of 906
REJ09B0292-0200