SH7616 Datasheet, PDF (255/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
Bit 23—CPU Condition Match Flag B (CMFCB): This flag is set to 1 when a CPU bus cycle
condition, among the break conditions set for channel B, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 23: CMFCB
0
1
Description
User break interrupt has not been generated by a channel B CPU cycle
condition
(Initial value)
User break interrupt has been generated by a channel B CPU cycle condition
Bit 22—DMAC Condition Match Flag B (CMFPB): This flag is set to 1 when an on-chip DMAC
bus cycle condition, among the break conditions set for channel B, is satisfied. This flag is not
cleared to 0 (if the flag setting is to be checked again after it has once been set, the flag must be
cleared by a write).
Bit 22: CMFPB
0
1
Description
User break interrupt has not been generated by a channel B on-chip DMAC
cycle condition
(Initial value)
User break interrupt has been generated by a channel B on-chip DMAC cycle
condition
Bit 21—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 20 and 19—Sequence Condition Select (SEQ1, SEQ0): These bits select independent or
sequential conditions for channels A, B, C, and D.
Bit 20:
SEQ1
0
1
Bit 19:
SEQ0
0
1
0
1
Description
Comparison based on independent conditions for channels A, B, C, and D
(Initial value)
Channel C → D sequential condition; channels A and B independent
Channel B → C → D sequential condition; channel A independent
Channel A → B → C → D sequential condition
Rev. 2.00 Mar 09, 2006 page 229 of 906
REJ09B0292-0200