SH7616 Datasheet, PDF (397/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 8 Cache
Address array read:
Bit
31 29 28
Address
011
—
Number of bits 3
19
Bit
31 29 28
Data
—
Number of bits 3
10 9
43 0
Entry
address
—
6
4
Tag address
19
10 9
43 2 1 0
LRU
information
—
V
—
6 11 2
Address array write:
Bit
Address
31 29 28
011
Number of bits 3
Bit
31
Data
Number of bits
Tag address
19
10 9
43 2 1 0
Entry
address
—V
—
6 11 2
10 9
43 0
—
LRU
information
—
22
6
4
V: Valid bit
Figure 8.13 Address Array Access
8.5 Cache Use
8.5.1 Initialization
Cache memory is not initialized in a reset. Therefore, the cache must be initialized by software
before use. The cache is initialized by zeroizing all address array valid bits and LRU information.
The address array write function can be used to initialize each line, but it is simpler to initialize it
once by writing 1 to the CP bit in CCR. Figure 8.14 shows how to initialize the cache.
MOV.W
MOV.B
AND
MOV.B
OR
MOV.B
OR
MOV.B
#H'FE92, R1
@R1, R0
;
#H'FE, R0 ;
#R0, @R1 ; Cache disable
#H'10, R0
R0, @R1
; Cache purge
#H'01, R0
R0, R1
; Cache enable
Figure 8.14 Cache Initialization
Rev. 2.00 Mar 09, 2006 page 371 of 906
REJ09B0292-0200