SH7616 Datasheet, PDF (135/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 3 Oscillator Circuits and Operating Modes
3.2.2 Clock Operating Mode Settings
Table 3.2 lists the functions and operation of clock modes 0 to 6.
Table 3.2 Operating Modes
Clock Mode
0
1
2
3
4
Function/Operation
Clock Source
PLL circuits 1 and 2 operate. A clock is output with the same Crystal resonator/
phase (with the same frequency as Eφ) as the internal clocks external clock input
(Iφ, Eφ, Pφ) from the CKIO pin
PLL circuits 1 and 2 can be switched between the operating
and halted states by means of control bits in the frequency
modification register (FMR). The CKIO pin can also be placed
in the high-impedance state
Normally, mode 0 should be used.
PLL circuits 1 and 2 operate. A clock (with the same
frequency as Eφ) 1/4 φ cycle in advance of the chip's internal
system clock φ is output from the CKIO pin.
PLL circuits 1 and 2 can be switched between the operating
and halted states by means of control bits in the frequency
modification register (FMR). The CKIO pin can also be placed
in the high-impedance state. However, clock phase shifting is
not performed when PLL circuit 1 is halted.
Normally, mode 0 should be used.
Only PLL circuit 2 operates. The clock from PLL circuit 2 is
output from the CKIO pin (having the same frequency as the
Eφ). As PLL circuit 1 does not operate, phases are not
matched in this mode
PLL circuit 2 can be switched between the operating and
halted states by means of a control bit in the frequency
modification register (FMR). The CKIO pin can also be placed
in the high-impedance state
Only PLL circuit 2 operates. The CKIO pin is high-impedance
PLL circuit 2 can be switched between the operating and
halted states by means of a control bit in the frequency
modification register (FMR)
Only PLL circuit 1 operates. Operate PLL circuit 1 when
operating with synchronization of the phases of the clock
input from the CKIO pin and the internal clocks (Iφ, Eφ, Pφ).
PLL circuit 2 does not operate in this mode
External clock input
PLL circuit 1 can be switched between the operating and
halted states by means of a control bit in the frequency
modification register (FMR)
Rev. 2.00 Mar 09, 2006 page 109 of 906
REJ09B0292-0200