SH7616 Datasheet, PDF (537/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Clock
Bus cycle
CPU
CPU
DMAC
CPU
DREQn
(Active high)
DACKn
(Active high)
1st
acceptance
Blind zone
Blind zone
2nd
acceptance
Requests acceptable
Figure 11.38 DREQn Pin Input Detection Timing in Cycle-Steal Mode with Level Detection
(Byte/Word/Longword Setting)
Clock
Bus cycle
CPU
CPU
DMAC
H
DMAC
L
DREQn
(Active high)
DACKn
(Active high)
Blind zone
1st
acceptance
Blind zone
2nd
acceptance
DACK
H
DACK
L
Figure 11.39 When a 16-Bit External Device is Connected (Level Detection)
Rev. 2.00 Mar 09, 2006 page 511 of 906
REJ09B0292-0200