SH7616 Datasheet, PDF (305/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
When the CMIE bit in RTCSR is set to 1, an interrupt request is sent to the controller by this
match signal. The interrupt request is output continuously until the CMF bit in RTCSR is cleared.
When the CMF bit clears, it only affects the interrupt; the refresh request is not cleared by this
operation. When a refresh is performed and refresh requests are counted using interrupts, a refresh
can be set simultaneously with the interval timer interrupt.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
7.3 Access Size and Data Alignment
7.3.1 Connection to Ordinary Devices
Byte, word, and longword are supported as access units. Data is aligned based on the data width of
the device. Therefore, reading longword data from a byte-width device requires four read
operations. The bus state controller automatically converts data alignment and data length between
interfaces. An 8-bit, 16-bit, or 32-bit external device data width can be connected by using the
mode pins for the CS0 space, or by setting BCR2 for the CS1–CS4 spaces. However, the data
width of devices connected to the respective spaces is specified statically, and the data width
cannot be changed for each access cycle. Figures 7.5 to 7.7 show the relationship between device
data widths and access units.
32-bit external device (ordinary)
A24–A0 ^D31
000000 7
000001
000002
000003
000000 15
000002
000000 31
D23
0
7
87
24 23
D15
0
7
0
15
16 15
D7
0
7
87
87
D0 _{Data input/output pin}
Byte read/write of address 0
Byte read/write of address 1
Byte read/write of address 2
0 Byte read/write of address 3
Word read/write of address 0
0 Word read/write of address 2
0 Longword read/write of address 0
Figure 7.5 32-Bit External Devices and Their Access Units
Rev. 2.00 Mar 09, 2006 page 279 of 906
REJ09B0292-0200