SH7616 Datasheet, PDF (118/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.31 shows the correspondence between the DSP data transfer operands and registers. CPU
core registers are used as pointer addresses indicating memory addresses.
Table 2.31 Correspondence between DSP Data Transfer Operands and Registers
SH (CPU Core) Registers
R4
R5
R8
Oper-
R2
R3
(Ax0) (Ax1) R6
R7
(Ix)
R9
and R0 R1 (As2) (As3) (As0) (As0) (Ay0) (Ay1) (Is)
(Iy)
Ax
———
—
Yes
Yes
—
—
—
—
Ix (Is) — — —
—
—
—
—
—
Yes
—
Dx
———
—
—
—
—
—
—
—
Ay
———
—
—
—
Yes
Yes
—
—
Iy
———
—
—
—
—
—
—
Yes
Dy
———
—
—
—
—
—
—
—
Da
———
—
—
—
—
—
—
—
As
— — Yes
Yes
Yes
Yes
—
—
—
—
Ds
———
—
—
—
—
—
—
—
Oper-
DSP Registers
and X0 X1 Y0
Y1
M0
M1
A0
A1
A0G A1G
Ax
———
—
—
—
—
—
—
—
Ix (Is) — — —
—
—
—
—
—
—
—
Dx
Yes Yes —
—
—
—
—
—
—
—
Ay
———
—
—
—
—
—
—
—
Iy
———
—
—
—
—
—
—
—
Dy
— — Yes
Yes
—
—
—
—
—
—
Da
———
—
—
—
Yes
Yes
—
—
As
———
—
—
—
—
—
—
—
Ds
Yes Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note: Yes indicates that the register can be set.
Rev. 2.00 Mar 09, 2006 page 92 of 906
REJ09B0292-0200