SH7616 Datasheet, PDF (9/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Item
Page
11.3.6 DMA Transfer 496
Request
Acknowledge Signal
Output Timing
Figure 11.13 Example
of DACKn Output
Timing
Revision (See Manual for Details)
Figure replaced
Clock
DACKn
(Active high)
0.5 cycles
Address bus
CPU
DMAC
14.3.4 Operation in 613
Synchronous Mode
15.4 SIOF Interrupt 663
Sources and DMAC
Table 15.3 SIOF 664
Interrupt Sources
Description amended
In synchronous mode, the SCIF receives data in synchronization
with the rise of the serial clock.
Description amended
Each SIOF channel has four interrupt sources: the receive-overrun-
error interrupt (RERI0) request, transmit-underrun-error interrupt
(TERI0) request, receive-data-full interrupt/receive-control-data-
register-full interrupt (RDFI0) request, and transmit-data-empty
interrupt/transmit-control-data-register-empty interrupt (TDEI0)
request. Table 15.3 shows the interrupt sources and their relative
priorities. The RDFI0 and TDEI0 interrupts are enabled by the RIE,
RCIE, TIE, and TCIE bits, respectively, in SICTR. The RERI0 and
TERI0 interrupts cannot be disabled.
Table amended
Interrupt
Source Description
DMAC
Activation Priority
RERI0 Receive overrun error (RERR)
Not possible High
TERI0
Transmit underrun error (TERR)
Not possible ^↑
RDFI0
TDEI0
Receive data register full (RDRF)/
Possible*
Receive Control Data Register Full (RCD)
↓
Transmit data register empty (TDRE)/
Possible* ^Low
Transmit Control Data Register Empty (TCD)
Appendix C
904
Table C.1 SH7616
Product Lineup
Table amended
Abbreviation Voltage
SH7616
3.3 V
Operating
Frequency
62.5 MHz
Mark Code
HD6417616SF
Package
PLQP0208KA-A
Rev. 2.00 Mar 09, 2006 page ix of xxvi