SH7616 Datasheet, PDF (694/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 16 Serial I/O (SIO)
16.2 Register Configuration
Table 16.2 shows the SIO’s registers. As the channels are independent, the channel numbers are
omitted from the signal names in the rest of this section.
Table 16.2 Register Configuration
Channel Register
Abbrevia-
tion
R/W
Initial
Value Address
Access Size
(Bits)
1
Receive shift register 1 SIRSR1 —
—
—
—
Receive data register 1 SIRDR1 R
H'0000 H'FFFFFC10 8, 16, 32
Transmit shift register 1 SITSR1 —
—
—
—
Transmit data register 1 SITDR1 R/W H'0000 H'FFFFFC12 8, 16, 32
Serial control register 1 SICTR1 R/W H'0000 H'FFFFFC14 8, 16, 32
Serial status register 1 SISTR1 R/(W)* H'0002 H'FFFFFC16 8, 16, 32
2
Receive shift register 2 SIRSR2 —
—
—
—
Receive data register 2 SIRDR2 R
H'0000 H'FFFFFC20 8, 16, 32
Transmit shift register 2 SITSR2 —
—
—
—
Transmit data register 2 SITDR2 R/W H'0000 H'FFFFFC22 8, 16, 32
Serial control register 2 SICTR2 R/W H'0000 H'FFFFFC24 8, 16, 32
Serial status register 2 SISTR2 R/(W)* H'0002 H'FFFFFC26 8, 16, 32
Note: * Only 0 should be written, to clear flags (after reading 1 from the flag).
Rev. 2.00 Mar 09, 2006 page 668 of 906
REJ09B0292-0200