SH7616 Datasheet, PDF (289/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
Bit 0—Synchronous DRAM Burst Write Specification (BWE): Enables burst write mode to be
specified when synchronous DRAM is specified for CS2 or CS3 space.
Bit 0: BWE
0
1
Description
Single write mode
Burst write mode
(Initial value)
7.2.4 Wait Control Register 1 (WCR1)
Bit:
Initial value:
R/W:
15
IW31
1
R/W
14
IW30
0
R/W
13
IW21
1
R/W
12
IW20
0
R/W
11
IW11
1
R/W
10
IW10
0
R/W
9
IW01
1
R/W
8
IW00
0
R/W
Bit:
Initial value:
R/W:
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
2
W10
1
R/W
1
W01
1
R/W
0
W00
1
R/W
Do not access a space other than CS0 until the settings for register initialization are completed.
Bits 15 to 8—Idles between Cycles for Areas 3 to 0 (IW31–IW00): These bits specify idle cycles
inserted between consecutive accesses to different CS spaces. Idles are used to prevent data
conflict between ROM or the like, which is slow to turn the read buffer off, and fast memories and
I/O interfaces. Even when access is to the same space, idle cycles must be inserted when a read
access is followed immediately by a write access. The idle cycles to be inserted comply with the
specification for the previously accessed space. The set values below show the minimum number
of idle cycles; more cycles than indicated by the Idles between Cycles setting may actually be
inserted.
IW31, IW21, IW11, IW01
0
1
IW30, IW20, IW10, IW00
0
1
0
1
Description
No idle cycle
One idle cycle inserted
Two idle cycles inserted
Four idle cycles inserted
(Initial value)
Rev. 2.00 Mar 09, 2006 page 263 of 906
REJ09B0292-0200