SH7616 Datasheet, PDF (725/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
17.2.4 Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Bit: 7
6
5
4
3
2
1
0
—
—
— TCIEV TGIED TGIEC TGIEB TGIEA
Initial value: 0
1
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
— TCIEU TCIEV —
1
0
0
0
R
R/W
R/W
R
2
1
0
— TGIEB TGIEA
0
0
0
R
R/W
R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has three TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset.
Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 6—Reserved: This bit is always read as 1. The write value should always be 1.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2.
In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5: TCIEU
0
1
Description
Interrupt requests (TCIU) by TCFU disabled
Interrupt requests (TCIU) by TCFU enabled
(Initial value)
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
Bit 4: TCIEV
0
1
Description
Interrupt requests (TCIV) by TCFV disabled
Interrupt requests (TCIV) by TCFV enabled
(Initial value)
Rev. 2.00 Mar 09, 2006 page 699 of 906
REJ09B0292-0200