SH7616 Datasheet, PDF (400/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 8 Cache
H'00000000
H'C0000000
H'C00003FF
H'C0000400
H'C00007FF
Way 0
Way 1
H'FFFFFFFF
Figure 8.16 Address Mapping of 2-kbyte RAM in the Two-Way Mode
8.6 Usage Notes
8.6.1 Standby
Disable the cache before entering the standby mode for power-down operation. After returning
from standby, initialize the cache before use.
8.6.2 Cache Control Register
Changing the contents of CCR also changes cache operation. The chip makes full use of pipeline
operations, so it is difficult to synchronize access. For this reason, change the contents of the cache
control register simultaneously when disabling the cache or after the cache is disabled. After
changing the CCR contents, perform a CCR read.
Rev. 2.00 Mar 09, 2006 page 374 of 906
REJ09B0292-0200