SH7616 Datasheet, PDF (719/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 17 16-Bit Timer Pulse Unit (TPU)
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR
registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized
to H'00 by a reset.
Note that TIOR is affected by the TMDR setting.
The initial output specified by TIOR becomes valid when the counter is halted (i.e. when the CST
bit is cleared to 0 in TSTR). In PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0)
I/O Control D3 to D0 (IOD3 to IOD0):
Bits IOB3 to IOB0 specify the function of TGRB.
Bits IOD3 to IOD0 specify the function of TGRD.
TIOR0H
Bit 7: Bit 6: Bit 5: Bit 4:
Channel IOB3 IOB2 IOB1 IOB0 Description
0
0
0
0
0
TGR0B is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
1
0
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
0
TGR0B is Capture input Input capture at rising edge
1
input
source is
Input capture at falling edge
1
*
capture TIOCB0 pin
register
Input capture at both edges
1
*
*
Setting prohibited
*: Don’t care
Rev. 2.00 Mar 09, 2006 page 693 of 906
REJ09B0292-0200