SH7616 Datasheet, PDF (458/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register.
An interrupt is enabled by writing 1 to the corresponding bit. In the initial state, interrupts are not
enabled.
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
— RFCOFIP
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 23
—
Initial value: 0
R/W: R
22
ECIIP
0
R/W
21
TCIP
0
R/W
20
TDEIP
0
R/W
19
TFUFIP
0
R/W
18
FRIP
0
R/W
17
RDEIP
0
R/W
16
RFOFIP
0
R/W
Bit: 15
14
13
12
11
10
9
8
—
—
—
ITFIP CNDIP DLCIP CDIP TROIP
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
RMAFIP — RFARIP RRFIP RTLFIP RTSFIP PREIP CERFIP
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Bits 31 to 25—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 24—Receive Frame Counter Overflow Interrupt Permission (RFCOFIP): Enables the receive
frame counter overflow interrupt.
Bit 24: RFCOFIP Description
0
Receive frame counter overflow interrupt is disabled
1
Receive frame counter overflow interrupt is enabled
(Initial value)
Rev. 2.00 Mar 09, 2006 page 432 of 906
REJ09B0292-0200