SH7616 Datasheet, PDF (424/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.17 Too-Short Frame Receive Counter Register (TSFRCR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit:
Initial value:
R/W:
15
14
13
12
11
10
TSFC15 TSFC14 TSFC13 TSFC12 TSFC11 TSFC10
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
9
TSFC9
0
R/W
8
TSFC8
0
R/W
Bit:
Initial value:
R/W:
7
TSFC7
0
R/W
6
TSFC6
0
R/W
5
TSFC5
0
R/W
4
TSFC4
0
R/W
3
TSFC3
0
R/W
2
TSFC2
0
R/W
1
TSFC1
0
R/W
0
TSFC0
0
R/W
TSFRCR is a 16-bit counter that indicates the number of frames of fewer than 64 bytes that have
been received. When the value in this register reaches H'FFFF (65,535), the count is halted. The
counter value is cleared to 0 by a write to this register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—Too-Short Frame Receive Count 15 to 0 (TSFC15 to TSFC0): These bits indicate
the count of frames received with a length of less than 64 bytes.
Rev. 2.00 Mar 09, 2006 page 398 of 906
REJ09B0292-0200