SH7616 Datasheet, PDF (605/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
SCSMR Settings
n
Clock
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
1
2
Pφ/16
1
0
3
Pφ/64
1
The bit rate error in asynchronous mode is found from the following equations:
Error (%) =
Pφ × 10⁶
(N + 1) × B × 64 × 2^{2n–1 – 1 × 100}
(When operating on a base clock of 16 times the bit rate)
Error (%) =
Pφ × 10⁶
(N + 1) × B × 32 × 2^{2n–1 – 1 × 100}
(When operating on a base clock of 8 times the bit rate)
Error (%) =
Pφ × 10⁶
(N + 1) × B × 16 × 2^{2n–1 – 1 × 100}
(When operating on a base clock of 4 times the bit rate)
Table 14.3 shows sample SCBRR settings in asynchronous mode, and table 14.4 shows sample
SCBRR settings in synchronous mode. In both tables, the values are for operation on a base clock
of 16 times the bit rate.
Rev. 2.00 Mar 09, 2006 page 579 of 906
REJ09B0292-0200