SH7616 Datasheet, PDF (669/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
Clear this bit to 0 if SIRCDR and SITCDR are not used, or if all interrupts triggered by the RDRF,
TDRE, RCD and TCD bits in SISTR are to be processed by the CPU. The initial value of this bit
is 0.
Bit 10: DMACE
0
1
Description
DMAC is activated by RDRF and TDRE interrupts
DMAC is not activated by RDRF and TDRE interrupts
(Initial value)
Bit 9—Transmit-Control-Data-Register-Empty Interrupt Enable (TCIE): Enables the transmit-
control-data-register-empty interrupt. The initial value of this bit is 0.
Bit 9: TCIE
0
1
Description
Transmit-control-data-register-empty interrupt disabled
Transmit-control-data-register-empty interrupt enabled
(Initial value)
Bit 8—Receive-Control-Data-Register-Full Interrupt Enable (RCIE): Enables the receive-control-
data-register-full interrupt. The initial value of this bit is 0.
Bit 8: RCIE
0
1
Description
Receive-control-data-register-full interrupt disabled
Receive-control-data-register-full interrupt enabled
(Initial value)
Bit 7—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 6—Transfer Mode Control (TM): Specifies whether the transmission synchronization signal is
to be input from an external source or generated internally by the chip. When this flag is cleared,
the transmission synchronization signal is STS pin input. When this flag is set, the transmission
synchronization signal is generated by the chip, and is output to an external device from the STS
pin. This bit does not affect reception.
Bit 6: TM
Description
0
External signal input from STS pin is used as transmission start indication
(Initial value)
1
Internal signal output from STS pin is used as transmission start indication
Note:
If the transmit mode bit (TRMD) in SIFCR is set to 1, this bit must be cleared to 0.
If TM is set to 1 and SE is set to 1 (interval mode), output of the sync signal stops at the
point at which bits T4 to T0 in SIFDR are cleared to 0 (data count of transmit data register is
zero). If TE remains set to 1 and data is written to SITDR, output of the sync signal resumes
when the value of T4 to T0 in SIFDR becomes H'01 or above.
Rev. 2.00 Mar 09, 2006 page 643 of 906
REJ09B0292-0200