SH7616 Datasheet, PDF (571/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 13 Watchdog Timer (WDT)
13.1.4 Register Configuration
Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 13.2 Register Configuration
Address
Name
Abbreviation R/W
Initial Value Write^*1
Read^*2
Watchdog timer
WTCSR
control/status register
R/(W)^*3 H'18
H'FFFFFE80 H'FFFFFE80
Watchdog timer
counter
WTCNT
Reset control/status RSTCSR
register
R/W
H'00
R/(W)^*3 H'1D
H'FFFFFE80 H'FFFFFE81
H'FFFFFE82 H'FFFFFE83
Notes: 1. Write by word access. It cannot be written by byte or longword access.
2. Read by byte access. The correct value cannot be read by word or longword access.
3. Only 0 can be written in bit 7 to clear the flag.
13.2 Register Descriptions
13.2.1 Watchdog Timer Counter (WTCNT)
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTCNT is an 8-bit read/write register. The method of writing to WTCNT differs from that of
most other registers to prevent inadvertent rewriting. See section 13.2.4, Notes on Register Access,
for details. When the timer enable bit (TME) in the watchdog timer control/status register
(WTCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock source
selected by clock select bits 2 to 0 (CKS2 to CKS0) in WTCSR. When the value of WTCNT
overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval
timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit in WTCSR.
WTCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. It is not initialized
in standby mode, when the clock frequency is changed, or in clock pause mode.
Rev. 2.00 Mar 09, 2006 page 545 of 906
REJ09B0292-0200