SH7616 Datasheet, PDF (587/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.1.4 Register Configuration
The SCIF has the internal registers shown in table 14.2. These registers are used to specify
asynchronous mode/synchronous mode and the IrDA communication mode, the data format and
the bit rate, and to perform transmitter/receiver control.
Table 14.2 SCIF Registers
Channel Name
Abbre-
viation
Initial
R/W Value
Address
Access
Size
1
Serial mode register
SCSMR1 R/W H'00
H'FFFFFCC0 8
Bit rate register
SCBRR1 R/W H'FF
H'FFFFFCC2 8
Serial control register
SCSCR1 R/W H'00
H'FFFFFCC4 8
Transmit FIFO data register
Serial status 1 register
Serial status 2 register
SCFTDR1
SC1SSR1
SC2SSR1
W
—
R/(W)^* H'0060
R/(W)^* H'20
H'FFFFFCC6 8
H'FFFFFCC8 16
H'FFFFFCCA 8
Receive FIFO data register SCFRDR1 R
Undefined H'FFFFFCCC 8
FIFO control register
SCFCR1 R/W H'00
H'FFFFFCCE 8
FIFO data count register
SCFDR1 R
H'0000 H'FFFFFCD0 16
FIFO error register
SCFER1 R
H'0000 H'FFFFFCD2 16
IrDA mode register
SCIFMR1 R/W H'00
H'FFFFFCD4 8
2
Serial mode register
SCSMR2 R/W H'00
H'FFFFFCE0 8
Bit rate register
SCBRR2 R/W H'FF
H'FFFFFCE2 8
Serial control register
SCSCR2 R/W H'00
H'FFFFFCE4 8
Transmit FIFO data register
Serial status 1 register
Serial status 2 register
SCFTDR2
SC1SSR2
SC2SSR2
W
—
R/(W)^* H'0060
R/(W)^* H'20
H'FFFFFCE6 8
H'FFFFFCE8 16
H'FFFFFCEA 8
Receive FIFO data register SCFRDR2 R
Undefined H'FFFFFCEC 8
FIFO control register
SCFCR2 R/W H'00
H'FFFFFCEE 8
FIFO data count register
SCFDR2 R
H'0000 H'FFFFFCF0 16
FIFO error register
SCFER2 R
H'0000 H'FFFFFCF2 16
IrDA mode register
SCIMR2 R/W H'00
H'FFFFFCF4 8
Note: * Only 0 can be written, to clear flags. Use byte access on registers with an access size of 8,
and word access on registers with an access size of 16.
Rev. 2.00 Mar 09, 2006 page 561 of 906
REJ09B0292-0200