SH7616 Datasheet, PDF (683/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
15.3.2 Output when TRMD = 0 in SIFCR
Figure 15.6 shows interval transfer mode when TM is cleared to 0 in SICTR and with MSB first.
Figure 15.7 shows continuous transfer mode when TM is cleared to 0 in SICTR and with MSB
first.
Figure 15.8 shows interval transfer mode when TM is set to 1 in SICTR and with MSB first.
Figure 15.9 shows continuous transfer mode when TM is set to 1 in SICTR and with MSB first.
Set to 1 when the amount of data in SITDR is
less than or equal to the setting of bits
TFWM3 to TFWM0 in SIFCR
TDRE
Synchronous internal clock
SITDR
C[7:0]
D[7:0]
Cleared to 0 when an amount of data exceeding
the setting of bits TFWM3 to TFWM0 in SIFCR
has been written to SITDR
D[7:0]
E[7:0]
SITSR
Undefined
C[7:0] C[6:0] C[5:0]
C[0]
D[7:0] D[6:0]
STCK
STS
STXD
C[7] C[6] C[5]
C[0]
D[7] D[6]
Note: TM = 0: STS is input
DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
LM = 0: MSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Figure 15.6 Transmission: Interval Transfer Mode (TM = 0 Mode)/MSB First
Rev. 2.00 Mar 09, 2006 page 657 of 906
REJ09B0292-0200