SH7616 Datasheet, PDF (395/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 8 Cache
When writing to or reading the address obtained by adding H'40000000 to the address to be
purged, the valid bit of the entry storing the address prior to addition are initialized to 0.
16 bytes are purged in each write, so a purge of 256 bytes of consecutive areas can be
accomplished in 16 writes. Access sizes when associative purges are performed should be
longword. A purge of 1 line requires 2 cycles.
Also note that write-back (flushing) to the main memory is not performed if there is a dirty line in
the cache.
Associative purge:
Bit
31 29 28
Address
010
Number of bits 3
Tag address
19
10 9
43 0
Entry
address
—
6
4
Figure 8.11 Associative Purge Access
8.4.8 Cache Flushing
When the CPU rewrites the contents of a specific shared address in the cache by write-back in a
multiprocessor configuration or a configuration in which the chip's internal E-DMAC (or DMAC)
and CPU share memory, the rewritten data must be written back to the main memory, and the
cache contents invalidated, before the bus is granted by the CPU in the chip to another master
(external master, E-DMAC, or DMAC). The chip does not support an instruction or procedure for
flushing the contents of specific addresses, so in order to execute a cache flush it is necessary to
perform reads in a 4-kbyte space (cache area) other than the address space to be flushed from
cache, and intentionally create cache misses. For this purpose, cache accesses should be performed
every 16 bytes. By this means, write-backs are generated and the contents written to the cache by
the CPU in the chip are written back to the main memory, enabling flushing to be executed.
However, this method incurs an overhead consisting of the cache fill time due to read misses and
the time for rereading data to be left in the cache. Therefore, if the overhead due to use of the
write-back method is of concern when constructing a system in which a number of masters share
memory, the shared area should be made a cache-through area in order to maintain coherency.
8.4.9 Data Array Access
The cache data array can be read or written directly via the data array read/write area. Byte, word,
or longword access can be used on the data array. Data array accesses are completed in 1 cycle for
a read and 2 cycles for a write. Since only the cache bus is used, the operation can proceed in
parallel even when another master, such as the DMAC, is using the bus. The data array of way 0 is
Rev. 2.00 Mar 09, 2006 page 369 of 906
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