SH7616 Datasheet, PDF (216/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.4 Interrupt Operation
5.4.1 Interrupt Sequence
The sequence of operations in interrupt generation is described below and illustrated in figure 5.8.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt among the interrupt requests sent,
according to the priority levels set in interrupt priority level setting registers A to E (IPRA–
IPRE). Lower-priority interrupts are held pending. If two or more of these interrupts have the
same priority level or if multiple interrupts occur within a single module, the interrupt with the
highest default priority or the highest priority within its IPR setting unit (as indicated in table
5.4) is selected.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3–I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3–I0, the request is held pending. If the request priority
level is higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and
sends an interrupt request signal to the CPU.
4. The CPU detects the interrupt request sent from the interrupt controller when it decodes the
next instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling.
5. Status register (SR) and program counter (PC) are saved onto the stack.
6. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in
the status register (SR).
7. When external vector mode is specified for the IRL/IRQ interrupt, the vector number is read
from the external vector number input pins (D7–D0).
8. The CPU reads the start address of the exception service routine from the exception vector
table entry for the accepted interrupt, jumps to that address, and starts executing the program
there. This jump is not a delayed branch.
Rev. 2.00 Mar 09, 2006 page 190 of 906
REJ09B0292-0200