SH7616 Datasheet, PDF (516/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
 Transfer between on-chip memory and external memory
 Transfer between on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-
DMAC, and EtherC) and on-chip peripheral module (excluding DMAC, BSC, UBC, cache,
E-DMAC, and EtherC)*
Note: * Access size permitted by peripheral module register used as transfer source or transfer
destination (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC).
Transfer requests can be auto-request, external requests, or on-chip peripheral module requests.
If the transfer request source is the SCIF, SIOF or SIO, an SCIF, SIOF or SIO register,
respectively, must be the transfer destination or transfer source (see table 11.6). For the
combination of the specifiable setting to perform data transfer using an external request
(DREQn), see table 11.9. Dual address mode outputs DACKn in either the read cycle or write
cycle. The acknowledge/transfer mode bit (AM) of the DMA channel control registers 0 and 1
(CHCR0 and 1) specifies whether DACK is output in either the read cycle or the write cycle.
Figure 11.9 shows the DMA transfer timing in dual address mode.
CKIO
A24–A0
Address output to
external memory space
CS
RD
WE
D31–D0
DACKn
BS
Read strobe signal to
external memory space
Write strobe signal to
external memory space
I/O data of external
memory space
DMAC acknowledge signal
(active-low)
Figure 11.9 DMA Transfer Timing in Dual Address Mode
(External Memory Space → External Memory Space, DACKn Output in Read Cycle)
Rev. 2.00 Mar 09, 2006 page 490 of 906
REJ09B0292-0200