SH7616 Datasheet, PDF (301/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Chip
A15
A14
A13
A2
CKIO
CKE
CSn
RAS
CAS
RD/WR
D31
D0
DQMUU/WE3
DQMUL/WE2
DQMLU/WE1
DQMLL/WE0
Section 7 Bus State Controller (BSC)
256 Mbit
(2 Mword × 32-bit × 4 Bank)
synchronous DRAM
BA1
BA0
A11
A0
CLK
CKE
CS
RAS
CAS
WE
I/O31
I/O0
DQMUU
DQMUL
DQMLU
DQMLL
Figure 7.4 256 Mbit Synchronous DRAM (8 Mword × 32 bit) Connection Example
Bit 6—Memory Data Size (SZ): For synchronous DRAM and DRAM space, the data bus width of
BCR2 is ignored in favor of the specification of this bit.
Bit 6: SZ
0
1
Description
Word (16 bits)
Longword (32 bits)
(Initial value)
Bit 3—Refresh Control (RFSH): This bit determines whether or not the refresh operation of
DRAM/synchronous DRAM is performed.
Bit 3: RFSH
0
1
Description
No refresh
Refresh
(Initial value)
Bit 2—Refresh Mode (RMODE): When the RFSH bit is 1, this bit selects normal refresh or self-
refresh. When the RFSH bit is 0, do not set this bit to 1. When the RFSH bit is 1, self-refresh
mode is entered immediately after the RMODE bit is set to 1. When the RFSH bit is 1 and this bit
Rev. 2.00 Mar 09, 2006 page 275 of 906
REJ09B0292-0200