SH7616 Datasheet, PDF (245/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.2.13 Break Address Register D (BARD)
BARDH
Bit
Initial value
Read/Write
15
BAD31
0
R/W
14
BAD30
0
R/W
13
BAD29
0
R/W
12
BAD28
0
R/W
11
BAD27
0
R/W
10
BAD26
0
R/W
9
BAD25
0
R/W
8
BAD24
0
R/W
Bit
Initial value
Read/Write
7
BAD23
0
R/W
6
BAD22
0
R/W
5
BAD21
0
R/W
4
BAD20
0
R/W
3
BAD19
0
R/W
2
BAD18
0
R/W
1
BAD17
0
R/W
0
BAD16
0
R/W
BARDL
Bit
Initial value
Read/Write
15
BAD15
0
R/W
14
BAD14
0
R/W
13
BAD13
0
R/W
12
BAD12
0
R/W
11
BAD11
0
R/W
10
BAD10
0
R/W
9
BAD9
0
R/W
8
BAD8
0
R/W
Bit
Initial value
Read/Write
7
BAD7
0
R/W
6
BAD6
0
R/W
5
BAD5
0
R/W
4
BAD4
0
R/W
3
BAD3
0
R/W
2
BAD2
0
R/W
1
BAD1
0
R/W
0
BAD0
0
R/W
Break address register D (BARD) consists of two 16-bit readable/writable registers: break address
register DH (BARDH) and break address register DL (BARDL). BARDH specifies the upper half
(bits 31 to 16) of the address used as a channel D break condition, and BARDL specifies the lower
half (bits 15 to 0). The address bus connected to the X/Y memory can also be specified as a break
condition by making a setting in the XYED bit/XYSD bit in break bus cycle register D (BBRD).
When XYED = 0, BAD31 to BAD0 specify the address. When XYED = 1, the upper 16 bits
(BAD31 to BAD16) of BARD specify the X address bus, and the lower 16 bits (BAD15 to BAD0)
specify the Y address bus. BARDH and BARDL are initialized to H'0000 by a power-on reset;
after a manual reset, their values are undefined.
Rev. 2.00 Mar 09, 2006 page 219 of 906
REJ09B0292-0200