SH7616 Datasheet, PDF (194/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.3.11 Vector Number Setting Register E (VCRE)
Vector number setting register E (VCRE) is a 16-bit read/write register that sets the 16-bit timer
pulse unit 0 (TPU0) TGR0A and TGR0B input capture/compare match interrupt vector numbers
(0–127).
VCRE is initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— TG0AV6 TG0AV5 TG0AV4 TG0AV3 TG0AV2 TG0AV1 TG0AV0
0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
— TG0BV6 TG0BV5 TG0BV4 TG0BV3 TG0BV2 TG0BV1 TG0BV0
0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—16-Bit Timer pulse unit 0 (TPU0) TGR0A Input Capture/Compare Match Interrupt
Vector Number 6 to 0 (TG0AV6–TG0AV0): These bits set the vector number for the 16-bit timer
pulse unit 0 (TPU0) TGR0A input capture/compare match interrupt. There are seven bits, so the
value can be set between 0 and 127.
Bits 6 to 0—16-Bit Timer pulse unit 0 (TPU0) TGR0B Input Capture/Compare Match Interrupt
Vector Number 6 to 0 (TG0BV6–TG0BV0): These bits set the vector number for the 16-bit timer
pulse unit 0 (TPU0) TGR0B input capture/compare match interrupt. There are seven bits, so the
value can be set between 0 and 127.
Rev. 2.00 Mar 09, 2006 page 168 of 906
REJ09B0292-0200