SH7616 Datasheet, PDF (346/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.5.9 Overlap Between Auto Precharge Cycle (Tap) and Next Access
If the CPU and DMAC or E-DMAC are accessed sequentially and the first access is to SDRAM
and also in the auto precharge mode, the auto precharge cycle (Tap) of the first access may overlap
the second access if the second access is to a different memory space or to a different bank of the
same SDRAM. (Even if the second access is to the normal space, there may be an overlap with the
Tap cycle.) For this reason, it appears for the number of cycles of the second access as if access
takes place sooner (by the number of Tap cycles) than it actually does. Specific cases in which an
overlap occurs are listed in table 7.7. Also, figure 7.35 shows is a conceptual diagram of an
overlap that occurs when memory spaces CS2 and CS3 are connected to SDRAM (table 7.7, No.
3).
Table 7.7 Cases of Overlap Between Tap Cycle and Next Access
No. First Access
Second Access
1 Space CS3, auto precharge Access to different space among CS0, CS1, CS2, and CS3
2 ^mode
Access to different bank in CS3
3 Space CS2, auto precharge Access to different space among CS0, CS1, CS2, and CS3
4 ^mode
Access to different bank in CS2
First access
to CS2 space
Tr
Tc
Td1
Td2
Td3
Td4
Tde
Tap
Tap
Second
access to
Tr
Tc
CS3 space
Overlap
Td1
Td2
Figure 7.35 Conceptual Diagram of Overlap (Conditions: SDRAM Connected to CS2 Space
(RAS Precharge Time Set to 2 Cycles) and SDRAM Connected to CS3 Space)
Rev. 2.00 Mar 09, 2006 page 320 of 906
REJ09B0292-0200