SH7616 Datasheet, PDF (658/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Note that although the SCIF stops transferring receive data to SCFRDR after receiving a break, the
receive operation continues, so if the FER and BRK flags are cleared to 0 they will be set to 1
again.
Sending a Break Signal: The TxD pin is a general I/O pin whose input/output direction and level
are determined by the I/O port data register (DR) and the control register (CR) of the pin function
controller (PFC). This fact can be used to send a break signal.
The DR value substitutes for the mark state until the PFC setting is made. The initial setting
should therefore be as an output port outputting 1.
To send a break signal during serial transmission, clear DR, then set the TxD pin as an output port
with the PFC.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state.
Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission
cannot be started when any of the receive error flags (ORER, PER3 to PER0, FER3 to FER0) is
set to 1, even if the TDFE flag is set to 1. Be sure to clear the receive error flags to 0 before
starting transmission.
Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous
mode, the SCIF operates on a base clock with a frequency of 16, 8, or 4 times the transfer rate.
In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth, fourth, or second base clock
pulse. The timing is shown in figure 14.25.
Rev. 2.00 Mar 09, 2006 page 632 of 906
REJ09B0292-0200