SH7616 Datasheet, PDF (100/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Operation
Classification Types Code
Function
No. of
Instructions
Logic
6
AND
Logical AND
14
operations
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit set
TST
Logical AND and T bit set
XOR
Exclusive OR
Shift
10
ROTCL One-bit left rotation with T bit
14
ROTCR One-bit right rotation with T bit
ROTL One-bit left rotation
ROTR One-bit right rotation
SHAL One-bit arithmetic left shift
SHAR One-bit arithmetic right shift
SHLL
One-bit logical left shift
SHLLn n-bit logical left shift
SHLR One-bit logical right shift
SHLRn n-bit logical right shift
Branch
9
BF
Conditional branch, conditional branch with delay 11
(Branch when T = 0)
BT
Conditional branch, conditional branch with delay
(Branch when T = 1)
BRA
Unconditional branch
BRAF Unconditional branch
BSR
Branch to subroutine procedure
BSRF Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
Rev. 2.00 Mar 09, 2006 page 74 of 906
REJ09B0292-0200