SH7616 Datasheet, PDF (511/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Transfer requests Waiting channel DMAC operation
1. Requests occur
in channels
0 and 1
2. Channel 1
transfer starts
0
3. Channel 1
transfer ends
Channel priority order
Priority
changes
1>0
0>1
6. Request occurs
in channel 0
None
4. Channel 0
transfer starts
5. Channel 0
transfer ends
7. Channel 0
transfer starts
Priority
changes
1>0
Waiting for
transfer request
None
Priority
8. Channel 0
does not change
1>0
transfer ends
Figure 11.5 Channel Priority in Round-Robin Mode
Rev. 2.00 Mar 09, 2006 page 485 of 906
REJ09B0292-0200