SH7616 Datasheet, PDF (639/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.3.4 Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex
communication using a common clock. Both the transmitter and the receiver also have a 16-stage
FIFO buffer structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 14.16 shows the general format for synchronous serial communication.
*
Serial clock
One unit of transfer data (character or frame)
*
LSB
MSB
Serial data Don’t care Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Don’t care
Note: * High except in continuous transmission/reception
Figure 14.16 Data Format in Synchronous Communication
(Example of LSB-First Transfer)
In synchronous serial communication, data on the communication line is output from one fall of
the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In serial communication, each character is output starting with the LSB and ending with the MSB,
or vice versa, according to the setting of the TLM bit in the serial status 2 register (SC2SSR).
After the last data is output, the communication line remains in the state of the last data.
In synchronous mode, the SCIF receives data in synchronization with the rise of the serial clock.
Rev. 2.00 Mar 09, 2006 page 613 of 906
REJ09B0292-0200